Publications HAL

2023

Conference papers

titre
On Using Cell-Aware Methodology for SRAM Bit Cell Testing
auteur
Xhesila Xhafa, Aymen Ladhar, Eric Faehn, Lorena Anghel, Gregory Di Pendina, Patrick Girard, Arnaud Virazel
article
ETS 2023 - 28th IEEE European Test Symposium, May 2023, Venezia, Italy. pp.1-4, ⟨10.1109/ETS56758.2023.10174118⟩
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2022

Conference papers

titre
Binary Bayesian Neural Networks for Efficient Uncertainty Estimation Leveraging Inherent Stochasticity of Spintronic Devices
auteur
Soyed Tuhin, Kamal Danouchi, Christopher Münch, Guillaume Prenat, Lorena Anghel, Mehdi B Tahoori, Bayesian Neural
article
17th ACM International Symposium on Nanoscale Architectures, Association for Computing machinery, Dec 2022, Virtual conference, United States. ⟨10.1145/3565478.3572536⟩
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2021

Conference papers

titre
Zero-Overhead Protection for CNN Weights
auteur
Stéphane Burel, Adrian Evans, Lorena Anghel
article
2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2021, Athens (virtual), Greece. ⟨10.1109/DFT52944.2021.9568363⟩
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https://hal.science/hal-03470345/file/opportunistic_parity_dfts%20%282%29.pdf BibTex

2020

Conference papers

titre
From 1.8V to 0.19V voltage bias on analog spiking neuron in 28nm UTBB FD-SOI technology
auteur
V. Cinçon, Elena Ioana Vatajelu, Lorena Anghel, Philippe Galy
article
EUROSOI-ULIS 2020, Sep 2020, Caen, France
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https://hal.science/hal-03001733/file/PID6400047.pdf BibTex
titre
A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System
auteur
Michele Portolan, R. Silveira Feitoza, G. Takam Tchendjou, V. Reynaud, K. Senthamarai Kannan, Manuel J. Barragan, Emmanuel Simeu, Paolo Maistri, Lorena Anghel, Régis Leveugle, Salvador Mir
article
2020 International Symposium on On-Line Testing and Robust System Design (IOLTS 2020), Jul 2020, Naples (Virtual Conference), Italy. ⟨10.1109/IOLTS50870.2020.9159721⟩
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https://hal.science/hal-02939302/file/2020-IOLTS20_2020_Invited.pdf BibTex

2019

Conference papers

titre
Rebooting Computing: The Challenges for Test and Reliability
auteur
Alberto Bosio, Ian O'Connor, G. Rodrigues, F. Lima, Elena Ioana Vatajelu, Giorgio Di Natale, Lorena Anghel, S. Nagarajan, M. R. Fieback, S. Hamdioui
article
2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2019, Noordwijk, Netherlands. pp.8138-8143, ⟨10.1109/DFT.2019.8875270⟩
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https://hal.science/hal-02462194/file/Rebooting_Computing__the_challenges_for_Test_and_Reliability.pdf BibTex
titre
Memory-Centric Neuromorphic Computing With Nanodevices
auteur
Damien Querlioz, Tifenn Hirtzlin, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Marc Bocquet, Jean-Michel Portal, Miguel Romera, Philippe Talatchian, Julie Grollier
article
Biomedical Circuits and Systems Conference (BiOCAS), Oct 2019, Nara, Japan. ⟨10.1109/BIOCAS.2019.8919010⟩
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https://hal.science/hal-02399731/file/Querlios_BIOCAS2019.pdf BibTex

2018

Conference papers

titre
Neuromorphic Computing - From Robust Hardware Architectures to Testing Strategies
auteur
Lorena Anghel, Giorgio Di Natale, Benoit Miramond, Elena Ioana Vatajelu, E. Vianello
article
26th IFIP IEEE International Conference on Very Large Scale Integration (VLSI SOC 2018), Oct 2018, Verona, Italy. pp.176-179, ⟨10.1109/VLSI-SoC.2018.8644897⟩
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titre
Resistive and spintronic RAMs: device, simulation, and applications
auteur
Elena Ioana Vatajelu, Lorena Anghel, Jean-Michel Portal, Marc Bocquet, Guillaume Prenat
article
IOLTS 2018 - IEEE 24th International Symposium on On-Line Testing And Robust System Design, Jul 2018, Platja d'Aro, Spain. pp.109-114, ⟨10.1109/IOLTS.2018.8474226⟩
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https://hal.science/hal-01976583/file/EIV2018.pdf BibTex

2017

Conference papers

titre
Test and reliability in approximate computing
auteur
Lorena Anghel, Mounir Benabdenbi, Alberto Bosio, Elena Ioana Vatajelu
article
IMSTW: International Mixed-Signal Testing Workshop, Jul 2017, Thessaloniki, Greece. ⟨10.1109/IMS3TW.2017.7995210⟩
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2016

Conference papers

titre
Synthesis and Performance Optimization of a Switching Nano-crossbar Computer
auteur
D. Alexandrescu, M. Altun, Lorena Anghel, A. Bernasconi, V. Ciriani, L. Frontini, Mehdi B. Tahoori
article
Euromicro Conference on Digital System Design (Euromicro DSD/SEAA'16), Aug 2016, Limassol, Cyprus
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titre
Multi-context Non-volatile Content Addressable Memory Using Magnetic Tunnel Junctions
auteur
E. Deng, Guillaune Prenat, Lorena Anghel, W. Zhao
article
12th ACM/IEEE International Symposium on Nanoscale Architectures (NANOARCH'16), Jul 2016, Beijing, China
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titre
Multi-context non-volatile content addressable memory using magnetic tunnel junctions
auteur
Erya Deng, Guillaune Prenat, Lorena Anghel, Weisheng S Zhao
article
Nanoarch, Jul 2016, Beijing, China
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titre
In-Situ Slack Monitors : Taking up the Challenge of On-die Monitoring of Variability and Reliability
auteur
A. Benhassain, S. Mhira, F. Cacho, V. Huard, Lorena Anghel
article
International Verification and Security Workshop, Jul 2016, Sant Feliu de Guixols, Spain
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titre
A Hybrid Algorithm to Conservatively Check the Robustness of Circuits
auteur
N. Thole, Lorena Anghel, G. Fey
article
IEEE European Test Symposium (ETS'16), May 2016, Amsterdam, Netherlands
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titre
System Failure Prediction with On-Chip Monitors
auteur
Lorena Anghel
article
Colloque National 2016 de GDR SOC-SIP, May 2016, Nantes, France
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titre
Early system failure prediction by using aging in situ monitors: Methodology of implementation and application results
auteur
Lorena Anghel, A. Benhassain, A. Sivadasan
article
IEEE 34th VLSI Test Symposium (VTS'16), Apr 2016, Las Vegas, NE, United States
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titre
Robustness of Timing in-situ Monitors for AVS Management
auteur
A. Benhassain, F. Cacho, V. Huard, S. Mhira, Lorena Anghel, C. Parthasarathy, A. Jain, A. Sivadasan
article
IEEE International Reliability Physics Semiconductor (IRPS'16), Apr 2016, Passadena, United States
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titre
Workload Impact on BTI HCI Induced Aging of Digital Circuits: A System level Analysis
auteur
A. Sivadasan, F. Cacho, A. Benhassain, V. Huard, Lorena Anghel
article
Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, Mar 2016, Dresden, Germany
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titre
Study of workload impact on BTI HCI induced aging of digital circuits
auteur
A. Sivadasan, F. Cacho, A. Benhassain, V. Huard, Lorena Anghel
article
Design Automation and Test in Europe (DATE'16), Mar 2016, Dresden, Germany
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titre
Moniteurs de fiabilité embarqués en technologie FDSOI: Implémentation et Applications
auteur
Lorena Anghel
article
Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes Embarqués Hétérogènes (FETCH'16), Jan 2016, Vilard de Lans, France
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2015

Conference papers

titre
Reliability Measurements with In Situ Aging Monitors in FDSOI Technology
auteur
Lorena Anghel
article
International Test Conference (ITC'15), Oct 2015, Anaheim, United States
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titre
Timing in-situ monitors: Implementation strategy and applications results
auteur
A. Benhassain, F. Cacho, V. Huard, M. Saliva, Lorena Anghel, C. Parthasarathy, A. Jain, F. Giner
article
IEEE Custom Integrated Circuits Conference (ICICC'16), Sep 2015, San Jose, CA, United States
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titre
Application-independent testing of multilevel interconnect in mesh-based FPGAs
auteur
Saif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel
article
IEEE 10th International Conference on Design and Technologies for Integrated System in Nanoscale (DTIS'15), Apr 2015, Naples, Italy. pp.1-6
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titre
Impact of Gate Oxide Breakdown in Logic Gates from 28nm FDSOI CMOS technology
auteur
M. Saliva, F. Cacho, C. Ndiaye, V. Huard, D. Angot, A. Bravaix, Lorena Anghel
article
IEEE International Reliability Physics Symposium (IRPS'15), Apr 2015, Monterrey, CA, United States. pp.CA.4.1 - CA.4.6
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titre
Digital circuits reliability with in-situ monitors in 28nm fully depleted SOI
auteur
M. Saliva, F. Cacho, V. Huard, X. Federspiel, D. Angot, A. Benhassain, A. Bravaix, Lorena Anghel
article
Design, Automation & Test in Europe Conference & Exhibition (DATE'15), Mar 2015, Grenoble, France. pp.441-446
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2014

Conference papers

titre
Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example
auteur
A. Steininger, V.S. Veeravalli, D. Alexandrescu, E. Costenaro, Lorena Anghel
article
32nd IEEE International Conference on Computer Design (ICCD'14), Oct 2014, Seoul, North Korea. pp.61-67
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titre
Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA
auteur
Saif-Ur Rehman, Adrien Blanchardon, Arwa Ben Dhia, Mounir Benabdenbi, Roselyne Chotin-Avot, Lirida Naviner, Lorena Anghel, Habib Mehrez, Emna Amouri, Zied Marrakchi
article
IEEE Computer Society Annual Symposium on VLSI (ISVLSI'14), Jul 2014, Tampa, FL, United States. pp.553-558, ⟨10.1109/ISVLSI.2014.66⟩
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titre
New Insight about Oxide Breakdown Occurrence at Circuit Level
auteur
M. Saliva, F. Cacho, V. Huard, D. Angot, M. Durand, X. Federspiel, M. Parra, A. Bravaix, Lorena Anghel, Philippe Blanc-Benon
article
IEEE International Reliability Physics Symposium (IRPS'14), Jun 2014, Waikoloa, HI, United States
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titre
Single Event Effects in Muller C-Elements and Asynchronous Circuits Over a Wide Energy Spectrum
auteur
Lorena Anghel, V. Savulimedu Veeravalli, D. Alexandrescu, A. Steininger, K. Schneider-Hornstein, E. Costenaro
article
The 10th IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE'14), Apr 2014, Stanford, United States
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titre
Efficient Fault-Tolerant Adaptive Routing under an unconstrained Set of Node and Link Failures for Many Cores System On Chip
auteur
M. Dimopoulos, Yi Gang, Mounir Benabdenbi, Lorena Anghel
article
Workshop on Dependable Multicore and Transactional Memory Systems (DMTM'14), (joint to HIPEAC event), Jan 2014, Vienna, Austria. pp.1-2
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2013

Conference papers

titre
BIST for Logic and Local Interconnect Resources in a Novel Mesh of Cluster FPGA
auteur
Saif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel
article
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2013, New-York, United States. pp.296 - 301, ⟨10.1109/DFT.2013.6653622⟩
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titre
Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip
auteur
M. Dimopulos, Yi Gang, Mounir Benabdenbi, Lorena Anghel, Nacer-Eddine Zergainoh, M. Nicolaidis
article
IEEE International On-Line Testing symposium (IOLTS'13), Jul 2013, Chania, Crete, France. pp.7-12, ⟨10.1109/IOLTS.2013.6604043⟩
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2012

Conference papers

titre
Through-Silicon-Via Built-In Self-Repair for Aggressive 3D Integration
auteur
M. Nicolaidis, V. Pasca, Lorena Anghel
article
IEEE 18th International On-Line Testing Symposium (IOLTS), Jun 2012, Sitges, Spain. pp.91-96, ⟨10.1109/IOLTS.2012.6313847⟩
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titre
Electromigration Behavior of 3D-IC TSV Interconnects
auteur
T. Frank, C. Chappaz, L. Arnaud, S. Moreau, P. Leduc, A. Thuaire, Lorena Anghel
article
62nd Electronic Components and Technology Conference (ECTC'12), May 2012, San Diego, CA, United States. pp.326 - 330
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titre
Efficient link-level error resilience in 3D NoCs
auteur
V. Pasca, Saif-Ur Rehman, Lorena Anghel
article
IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS'12), Apr 2012, Tallinn, Estonia. pp.127-132, ⟨10.1109/DDECS.2012.6219038⟩
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titre
A predictive bottom-up hierarchical approach to digital system reliability
auteur
V. Huard, E. Pion, F. Cacho, D. Croain, V. Robert, R. Delater, P. Mergault, Sylvain Engels, Lorena Anghel, N.R. Amador
article
IEEE International Reliability Physics Symposium (IRPS'12), Apr 2012, Anaheim, CA, United States. pp.4B.1.1 - 4B.1.10, ⟨10.1109/IRPS.2012.6241830⟩
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titre
Electromigration degradation mechanism analysis of SnAgCu interconnects for eWLB package
auteur
T. Frank, C. Chappaz, L. Arnaud, X. Federspiel, F. Colella, E. Petitprez, Lorena Anghel
article
IEEE International Reliability Physics Symposium (IRPS'12), Apr 2012, Anaheim, CA, United States. pp.2E.5.1 - 2E.5.6, ⟨10.1109/IRPS.2012.6241792⟩
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titre
Design for Test and Reliability in Ultimate CMOS
auteur
M. Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Y. Zorian, T. Karnik, K. Bowman, J. Tschanz, S.-L. Lu, C. Tokunaga, A. Raychowdhury, M. Khellah, J. Kulkarini, De Vivek, D. Avresky
article
Design, Automation and Test in Europe (DATE'12), Mar 2012, Dresden, Germany. pp.677-682
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titre
Towards Low-cost Soft Error Mitigation in SRAM-based FPGAs: a Case Study on AT40K
auteur
J. Ferron, Lorena Anghel, Régis Leveugle
article
3rd IEEE Latin American Symposium on Circuits and Systems (LASCAS'12), Feb 2012, Playa del Carmen, Mexico
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titre
On the Dependability of 3D Interconnects
auteur
Lorena Anghel
article
Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'12), Jan 2012, Alpes d'Huez, France
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2011

Conference papers

titre
Designing cost-effective robust systems by accurate reliability modeling
auteur
Lorena Anghel, V. Huard
article
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'11), Oct 2011, Vancouver, Canada
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titre
Analysis of configuration bit criticality in designs implemented with SRAM-based FPGAs
auteur
J. Ferron, Lorena Anghel, Régis Leveugle
article
IEEE Symposium on Industrial Electronics & Applications (ISIEA'11), Sep 2011, Langkawi, Malaysia. pp.83-88
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titre
Bottom-up digital system-level reliability modeling
auteur
N.R. Amador, V. Huard, E. Pion, F. Cacho, D. Croain, V. Robert, Sylvain Engels, Philippe Flatresse, Lorena Anghel
article
Custom Integrated Circuits Conference (CICC'11), Sep 2011, San Jose, Ca., United States. pp.1 - 4, ⟨10.1109/CICC.2011.6055343⟩
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titre
Electromigration Behavior of 3D-IC TSV
auteur
T. Frank, C. Chappaz, P. Leduc, L. Arnaud, S. Moreau, Aurélie Thuaire, F. Lorut, Lorena Anghel
article
Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D IC), in conjuction with ITC, Sep 2011, Anaheim, United States
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titre
Memory BIST with address programmability
auteur
A. Fradi, M. Nicolaidis, Lorena Anghel
article
IEEE international On Line Testing Symposium (IOLT'11), Jul 2011, Athenes, Greece. pp.79 - 85, ⟨10.1109/IOLTS.2011.5993815⟩
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titre
On the Dependability of 3D Interconnects
auteur
Lorena Anghel, M. Nicolaidis, V. Pasca
article
Dependability Issues in Deep-submicron Technologies Workshop (DDT'11), May 2011, Trondheim, Norway
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titre
I-BIRAS: Interconnect Built-In Self-Repair and Adaptive Serialization in 3D Integrated Systems
auteur
M. Nicolaidis, V. Pasca, Lorena Anghel
article
16th IEEE European Test Symposium (ETS'11), May 2011, Trondheim, Norway. pp.208 - 208, ⟨10.1109/ETS.2011.37⟩
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titre
Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor
auteur
H. Yu, M. Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh
article
16th IEEE European Test Symposium (ETS'11), May 2011, Trondheim, Norway. pp.93 - 98, ⟨10.1109/ETS.2011.20⟩
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titre
Criticality of Configuration Bits in SRAM-based FPGAs: Predictive Analysis and Experimental Results
auteur
Lorena Anghel, J. Ferron, Régis Leveugle
article
Workshop on Design for Reliability and Variability (DRVW'11), May 2011, Dana Point, CA, United States
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titre
Resistance Increase Due to Electromigration Induced Depletion Under TSV
auteur
T. Frank, C. Chappaz, P. Leduc, L. Arnaud, S. Moreau, Aurélie Thuaire, R. El Farhane, F. Lorut, Lorena Anghel
article
IEEE International Reliability Physics Symposium (IRPS'11), Monterey, CA, USA, April 10-14, Apr 2011, Monterey, ca., United States. pp.3F.4.1 - 3F.4.6, ⟨10.1109/IRPS.2011.5784499⟩
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titre
Configurable Thru-Silicon-Via interconnect Built-In Self-Test and diagnosis
auteur
V. Pasca, Lorena Anghel, Mounir Benabdenbi
article
IEEE Latin America Test Symposium Workshop (LATW'11), Mar 2011, Porto de Galinhas (PE), Brazil. pp.1-6, ⟨10.1109/LATW.2011.5985896⟩
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2010

Conference papers

titre
Reliability approach of high density Through Silicon Via (TSV)
auteur
T. Frank, C. Chappaz, P. Leduc, L. Arnaud, S. Moreau, Aurélie Thuaire, R. El Farhane, Lorena Anghel
article
12th Electronics Packaging Technology Conference (EPTC'10), Dec 2010, Singapore, Singapore. pp.321 - 324, ⟨10.1109/EPTC.2010.5702655⟩
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titre
I-BIRAS: « Interconnect Built-In Self-Repair and Adaptive-Serialization
auteur
M. Nicolaidis, Lorena Anghel, V. Pasca
article
International Test Conference Workshop on Test of 3D Stacked Systems (3D-TEST), Nov 2010, Austin, TX, United States
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titre
Interconnect Built-In Self-Repair and Adaptive-Serialization (I-BIRAS) for 3D integrated systems
auteur
M. Nicolaidis, V. Pasca, Lorena Anghel
article
IEEE International On-Line Testing Symposium (IOLTS'10), Jul 2010, Corfu, Greece. pp.218 - 218, ⟨10.1109/IOLTS.2010.5560198⟩
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titre
Configurable Serial Fault-Tolerant Link for Communication in 3D Integrated Systems
auteur
V. Pasca, Lorena Anghel, C. Rusu, Mounir Benabdenbi
article
International On-Line Test Symposium (IOLTS'10), Jul 2010, Corfu, Greece. pp.115-120
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titre
RILM: Reconfigurable inter-layer routing mechanism for 3D multi-layer networks-on-chip
auteur
C. Rusu, Lorena Anghel, D. Avresky
article
International On-Line Test Symposium (IOLTS'10), Jul 2010, Corfu, Greece. pp.121-125
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titre
Fault Tolerant Communication in 3D Integrated Systems
auteur
V. Pasca, Lorena Anghel, Mounir Benabdenbi
article
DSN Workshop on Dependable Systems and Networks (WDSN'10), Jun 2010, Chicago, United States. pp.131-135
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titre
Non-regular 3D mesh Networks-on-Chip
auteur
V. Pasca, Lorena Anghel, C. Rusu, Mounir Benabdenbi
article
DAC Workshop on Diagnostic Services in Network-on-Chips (DSNoC'10), Jun 2010, Anaheim, United States
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titre
Configurable Fault-Tolerant Link for Inter-die Communication in 3D on-Chip Networks
auteur
V. Pasca, Lorena Anghel, C. Rusu, Mounir Benabdenbi
article
European Test Symposium (ETS'10), May 2010, Prague, Czech Republic. pp.258
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titre
Fault Resilient Intra-die and Inter-die Communication in 3D Integrated Systems
auteur
V. Pasca, Lorena Anghel, Mounir Benabdenbi
article
PhD Research in Microelectronics and Electronics Conference, PRIME 2010, May 2010, Berlin, Germany
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titre
Error Resilience of Inter-Die and Intra-Die Communication with 3D Spidergon STNoC
auteur
V. Pasca, Lorena Anghel, C. Rusu, R. Locatelli, M. Coppola
article
Design Automation and Test in Europe Conference, (DATE'10), Mar 2010, Dresden, Germany. pp.275-278
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titre
Checkpoint and rollback recovery in network-on-chip based systems
auteur
C. Rusu, Lorena Anghel
article
Student forum at 15th Asia and South Pacific Design Automation Conference (ASP-DAC'10), Jan 2010, Taipei, Taiwan
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2009

Conference papers

titre
Message routing in 3D networks-on-chip
auteur
C. Rusu, Lorena Anghel, D. Avresky
article
NORCHIP Conference 2009, Nov 2009, Trondheim, Norway
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titre
A methodology and tool for predictive analysis of configuration bit criticality in SRAM-based FPGAs: experimental results
auteur
J. Ferron, Lorena Anghel, Régis Leveugle, A. Bocquillon, F. Miller, G. Mantelet
article
3rd International Conference on Signals, Circuits & Systems (SCS), Nov 2009, Djerba, Tunisia
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titre
Predictive analysis of configuration bit criticality in SRAM-based FPGAs – Methodology, tools, and results
auteur
J. Ferron, Lorena Anghel, Régis Leveugle
article
3ème Colloque du GdR SoC-SiP, Jun 2009, Paris, France
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titre
An Effective Approach to Detect Logic Soft Errors in Digital Circuits Based on GRAAL
auteur
H. Yu, M. Nicolaidis, Lorena Anghel
article
10th International Symposium on Quality of Electronic Design (ISQED'09), Mar 2009, San Jose, CA, United States. pp.236-240, ⟨10.1109/ISQED.2009.4810300⟩
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2008

Conference papers

titre
Efficient Coordinated Checkpointing Recovery Schemes for Network-on-Chip based Systems
auteur
C. Rusu, C. Grecu, Lorena Anghel
article
2nd International Workshop on Dependable Circuit Design (DECIDE'08), Nov 2008, Playa del Carmen, Mexico, Mexico
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titre
A flexible network-on-chip simulator for early design space exploration
auteur
C. Grecu, A. Ivanov, S. Saleh, C. Rusu, Lorena Anghel, Pande P.P., V. Nuca
article
1st Microsystems and Nanoelectronics Research Conference (MNRC 2008), Oct 2008, Ottawa, Canada. pp.33-36, ⟨10.1109/MNRC.2008.4683371⟩
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titre
Communication Aware Recovery Configurations for Networks-on-Chip
auteur
C. Rusu, C. Grecu, Lorena Anghel
article
14th IEEE International Symposium On-Line Testing (IOLT'08), Jul 2008, Rhodes, Greece. pp.201-206, ⟨10.1109/IOLTS.2008.44⟩
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titre
Blocking and Non-blocking Checkpointing for Networks-on-Chip
auteur
C. Rusu, C. Grecu, Lorena Anghel
article
2nd IEEE Workshop on Dependable and Secure Nanocomputing (WDSN'08), Jun 2008, Anchorage, Alaska, United States
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titre
SET-Factor: An Analysis and Design Tool to Reduce SET Sensitivity in Integrated Circuits
auteur
C. Lazzari, T. Assis, F. Kastensmidt, G. Wirth, Lorena Anghel, Ricardo Reis
article
13th IEEE European Test Symposium (ETS'08), May 2008, Verbania, Italy
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titre
Improving the Scalability of Checkpoint Recovery for Networks-on-Chip
auteur
C. Rusu, C. Grecu, Lorena Anghel
article
IEEE International Symposium on Circuits and Systems (ISCAS'08), Seattle, May 2008, Washington, United States. pp.2793-2796, ⟨10.1109/ISCAS.2008.4542037⟩
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titre
Structures robustes pour circuits logiques à base de CNTFET
auteur
T. Dang, Lorena Anghel, Régis Leveugle
article
11ème Journées Nationales du Réseau Doctoral en Microélectronique (JNRDM'08), May 2008, Bordeaux, France. pp.66
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titre
Coordinated versus Uncoordinated Checkpoint Recovery for Network-on-Chip based Systems
auteur
C. Rusu, C. Grecu, Lorena Anghel
article
4th IEEE International Symposium on Electronic Design, Test and Applications (DELTA'08), Jan 2008, Hong Kong, China. pp.32-37, ⟨10.1109/DELTA.2008.75⟩
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2007

Conference papers

titre
CNTFET-based CMOS-like gates and dispersion of characteristics
auteur
T. Dang, Lorena Anghel, V. Pasca, Régis Leveugle
article
International Design and Test Workshop (IDT'07), Dec 2007, Cairo, Egypt. pp.151-156
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titre
Efficient Transistor Sizing for Soft Error Protection in Combinational Logic Circuits
auteur
C. Lazzari, F. Lima, Lorena Anghel, Ricardo Reis
article
2nd International Workshop on Dependable Circuit Design (DECIDE’07), Dec 2007, Buenos Aires, Argentina
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titre
Efficient Timing Closure with a Transistor Level Design Flow
auteur
C. Lazzari, Cr. Santos, A. Ziesemer, Lorena Anghel, Ricardo Reis
article
IFIP International Conference on Very Large Scale Integration (VLSI-SoC'07), Oct 2007, Atlanta, GA, United States. pp.312-315
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titre
Essential Fault-Tolerance Metrics for NoC Infrastructures
auteur
C. Grecu, Lorena Anghel, Pande P.P., A. Ivanov, R. Saleh
article
IEEE International On-Line Test Symposium (IOLT'07), Jul 2007, Crete, Greece. pp.37-42, ⟨10.1109/IOLTS.2007.31⟩
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titre
Multiple Event Transient Induced by Nuclear Reactions in CMOS Logic Cells
auteur
C. Rusu, A. Bougerol, Lorena Anghel, C. Weulerse, N. Buard, S. Benhammadi, N. Renaud, Frédéric Wrobel, T. Carriere
article
13th IEEE International On-Line Testing symposium (IOLT'07), Jul 2007, Crete, Greece. pp.137-145, ⟨10.1109/IOLTS.2007.46⟩
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titre
Defect Tolerant Logic Gates for Unreliable Future Nanotechnologies
auteur
Lorena Anghel, M. Nicolaidis
article
International Conference on Artificial Neural Networks (IWANN), Jun 2007, San Sebastian, Spain. pp.422-429, ⟨10.1007/978-3-540-73007-1⟩
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titre
CNTFET-based logic gates and characteristics
auteur
T. Dang, Lorena Anghel, Régis Leveugle
article
Silicon Nanoelectronics Workshop (SNW'07), Jun 2007, Kyoto, Japan. pp.2
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titre
Defects Tolerant Logic Gates for Unreliable Future Nanotechnologies
auteur
Lorena Anghel, M. Nicolaidis
article
Special Session of International Work-Conference on Artificial Neural Networks (IWANN'07), Jun 2007, San Sebastian, Spain
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titre
SET fault injection methods in analog circuits: case study
auteur
A. Ammari, Lorena Anghel, Régis Leveugle, C. Lazzari, Ricardo Reis
article
8th Latin-American Test Workshop (LATW'07), Mar 2007, Cuzco, Peru. pp.155-160
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titre
Tools and methodology development for pulsed laser fault injection in SRAM-based FPGAs
auteur
V. Pouget, A. Douin, D. Lewis, P. Fouillat, G. Foucard, P. Peronnard, V. Maingot, J. Ferron, Lorena Anghel, Régis Leveugle, Raoul Velazco
article
8th Latin-American Test Workshop (LATW'07), 2007, Cuzco, Peru. pp.Session 8
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2006

Conference papers

titre
CNTFET-based logic gates and simulation
auteur
T. Dang, Lorena Anghel, Régis Leveugle
article
IEEE International Design and Test Workshop (IDT'06, Nov 2006, Dubai, United Arab Emirates. 6 p
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titre
SET and SEU effects at multiple abstraction levels
auteur
Lorena Anghel
article
Single Event Effects Symposium (SEE'06), Jun 2006, Long Beach, CA,, United States
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titre
Multiple Defects Tolerant Devices for Unreliable Future Nanotechnologies
auteur
C. Lazzari, Lorena Anghel, M. Nicolaidis
article
IEEE Latin American Test Workshop (LATW'06), Mar 2006, Buenos Aires, Argentina
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titre
CNTFET basics and simulation
auteur
T. Dang, Lorena Anghel, Régis Leveugle
article
Design and Test of Integrated Systems (DTIS'06), 2006, Tunis, Tunisia. pp.28-33
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titre
Prediction of transients induced by neutrons/protons in CMOS combinational logic cells
auteur
A. Hubert, A. Bougerol, F. Miller, N. Buard, Lorena Anghel, T. Carriere, Frédéric Wrobel, R. Gaillard
article
12th IEEE International On-Line Testing Symposium (IOLTS'06), 2006, Lake Como, Italy. 9 pp., ⟨10.1109/IOLTS.2006.51⟩
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titre
Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study
auteur
C. Lazzari, Ricardo Reis, Lorena Anghel
article
12th IEEE International On-Line Testing Symposium (IOLTS'06), 2006, Lake Como, Italy. pp.165-172, ⟨10.1109/IOLTS.2006.48⟩
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2005

Conference papers

titre
Transient and permanent fault tolerance memory cells for unreliable future nanotechnologies
auteur
Lorena Anghel, E. Kolonis, M. Nicolaidis
article
IEEE Latin American Test Workshop (LATW'05), Mar 2005, Salvador Bahia, Brazil. pp.187-192
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titre
Soft error circuit hardening techniques implementation using an automatic layout generator
auteur
C. Lazzari, Lorena Anghel, Ricardo Reis
article
Proceedings of IEEE Latin American Test Workshop (LATW'05), Mar 2005, Salvador Bahia, Brazil. pp.175-180
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titre
Evaluation of SET and SEU effects at multiple abstraction levels
auteur
Lorena Anghel, Régis Leveugle, Pierre Vanhauwaert
article
11th-IEEE-International-On-Line-Testing-Symposium., 2005, French Riviera, France. pp.309-12, ⟨10.1109/IOLTS.2005.28⟩
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titre
Simulation and mitigation of single event effects
auteur
Lorena Anghel, M. Nicolaidis
article
11th-IEEE-International-On-Line-Testing-Symposium, 2005, French Riviera, France. pp.81, ⟨10.1109/IOLTS.2005.65⟩
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titre
On implementing a soft error hardening technique by using an automatic layout generator: case study
auteur
C. Lazzari, Lorena Anghel, Ricardo Reis
article
11th-IEEE-International-On-Line-Testing-Symposium., 2005, French Riviera, France. pp.29-34, ⟨10.1109/IOLTS.2005.45⟩
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2004

Conference papers

titre
A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies
auteur
M. Nicolaidis, M.N. Achouri, Lorena Anghel
article
22nd IEEE VLSI Test Symposium, 2004, Napa Valley, United States. pp.313, ⟨10.1109/VTEST.2004.1299258⟩
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titre
Evaluation of Memory Built-in Self Repair Techniques for High Defect Density Technologies
auteur
Lorena Anghel, M. Nicolaidis, M.N. Achouri
article
10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC'04), 2004, Tahiti, Papeete French Polynesia, France. pp.315-320, ⟨10.1109/PRDC.2004.1276581⟩
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titre
Coupling Different Methodologies to Validate Obsolete Microprocessors
auteur
Lorena Anghel, Raoul Velazco, E. Sanchez, M. Sonza Reorda, G. Squillero
article
19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04), 2004, Cannes, France. pp.250-255, ⟨10.1109/DFT.2004.21⟩
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2003

Conference papers

titre
A Methodology for Test Replacement Solutions of Obsolete Processors
auteur
Raoul Velazco, Lorena Anghel, S. Saleh
article
9th IEEE International On-Line Testing Symposium, 2003, Kos International Convention Center, Kos Island, Greece. pp.209, ⟨10.1109/OLT.2003.1214400⟩
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titre
Preliminary Validation of an Approach Dealing with Processor Obsolescence
auteur
Lorena Anghel, Raoul Velazco, S. Saleh, S. Deswaertes, A. El Moucary
article
18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003, Boston, Cambridge, Ma, United States. pp.493, ⟨10.1109/DFTVS.2003.1250148⟩
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titre
A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities
auteur
M. Nicolaidis, M.N. Achouri, Lorena Anghel
article
18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003, Boston, Cambridge, Ma,, United States. pp.459, ⟨10.1109/DFTVS.2003.1250144⟩
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titre
Memory Built-In Self-Repair for Nanotechnologies
auteur
M. Nicolaidis, M.N. Achouri, Lorena Anghel
article
9th IEEE International On-Line Testing Symposium, 2003, Kos International Convention Center, Kos Island, Greece. pp.94-8, ⟨10.1109/OLT.2003.1214373⟩
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2002

Conference papers

titre
Simulating single event transients in DVSM ICs for ground level radiation
auteur
D. Alexandrescu, M. Nicolaidis, Lorena Anghel
article
3rd IEEE Latin American Test Workshop (LATW'02), Feb 2002, Montevideo, Uruguay
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titre
New methods for evaluating the impact of single event transients in VDSM ICs
auteur
D. Alexandrescu, Lorena Anghel, M. Nicolaidis
article
Proceedings-17th-IEEE-International-Symposium-on-Defect-and-Fault-Tolerance-in-VLSI-Systems.-DFT-2002, 2002, Vancouver, BC, Canada. pp.99-107, ⟨10.1109/DFTVS.2002.1173506⟩
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