Publications HAL du projet européen 687973

2020

Conference papers

titre
A universal spintronic technology based on Multifunctional Standardized Stack
auteur
Mehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Lionel Torres, Sophiane Senni, Guillaume Patrigeon, Pascal Benoit, Gregory Di Pendina, Guillaume Prenat
article
DATE 2020 - 23rd Design, Automation and Test in Europe Conference and Exhibition, Mar 2020, Grenoble, France. pp.394-399, ⟨10.23919/DATE48585.2020.9116321⟩
Accès au texte intégral et bibtex
https://hal.science/hal-03753403/file/2020_DATE_A_Universal_Spintronic_Technology_based_on_Multifunctional_Standardized_Stack.pdf BibTex

2018

Conference papers

titre
FPGA-based platform for fast accurate evaluation of Ultra Low Power SoC
auteur
Guillaume Patrigeon, Pascal Benoit, Lionel Torres
article
PATMOS: Power and Timing Modeling, Optimization and Simulation, Jul 2018, Platja d'Aro, Spain. pp.123-128, ⟨10.1109/PATMOS.2018.8464173⟩
Accès au texte intégral et bibtex
https://hal-lirmm.ccsd.cnrs.fr/lirmm-01890567/file/FPGA-based%20platform%20for%20fast%20accurate%20evaluation%20of%20Ultra%20Low%20Power%20SoC%20-%20D.pdf BibTex

2017

Conference papers

titre
A novel SRAM -STT-MRAM hybrid cache implementation improving cache performance
auteur
Odilia Coi, Guillaume Patrigeon, Sophiane Senni, Lionel Torres, Pascal Benoit
article
NANOARCH: Nanoscale Architectures, Jul 2017, Newport, United States. pp.39-44, ⟨10.1109/NANOARCH.2017.8053704⟩
Accès au texte intégral et bibtex
https://hal-lirmm.ccsd.cnrs.fr/lirmm-01548938/file/A%20novel%20SRAM%20-%20STT-MRAM%20hybrid%20cache%20implementation%20improving%20cache%20performance%20-%20C.pdf BibTex