Publications HAL

2024

Journal articles

ref_biblio
Alexandre Honorat, Mickaël Dardaillon, Hugo Miomandre, Jean-François Nezan. Automated Buffer Sizing of Dataflow Applications in a High-Level Synthesis Workflow. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2024, 17 (1), pp.1-26. ⟨10.1145/3626103⟩. ⟨hal-04237266⟩
Accès au texte intégral et bibtex
https://hal.science/hal-04237266/file/main.pdf BibTex

2023

Journal articles

ref_biblio
Alexandre Honorat, Hai Nam Tran, Thierry Gautier, Loïc Besnard, Shuvra S. Bhattacharyya, et al.. Real-Time Fixed Priority Scheduling Synthesis using Affine DataFlow Graphs: from Theory to Practice. ACM Transactions on Embedded Computing Systems (TECS), 2023, pp.1-30. ⟨10.1145/3615586⟩. ⟨hal-04200195⟩
Accès au texte intégral et bibtex
https://hal.science/hal-04200195/file/memocode23.pdf BibTex

Conference papers

ref_biblio
Pascal Fradet, Alain Girault, Alexandre Honorat. Sequential Scheduling of Dataflow Graphs for Memory Peak Minimization. LCTES 2023 - 24th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems, Jun 2023, Orlando (FL), United States. pp.76-86, ⟨10.1145/3589610.3596280⟩. ⟨hal-04163123⟩
Accès au texte intégral et bibtex
https://hal.science/hal-04163123/file/main.pdf BibTex

2022

Conference papers

ref_biblio
Alexandre Honorat, Thomas Bourgoin, Hugo Miomandre, Karol Desnos, Daniel Menard, et al.. Influence of Dataflow Graph Moldable Parameters on Optimization Criteria. DASIP 2022 - Workshop on Design and Architectures for Signal and Image Processing, Jun 2022, Budapest, Hungary. pp.83-95, ⟨10.1007/978-3-031-12748-9_7⟩. ⟨hal-03752645⟩
Accès au texte intégral et bibtex
https://hal.science/hal-03752645/file/dasip22.pdf BibTex

2021

Conference papers

ref_biblio
Hai Nam Tran, Alexandre Honorat, Shuvra S Bhattacharyya, Jean-Pierre Talpin, Thierry Gautier, et al.. A Framework for Fixed Priority Periodic Scheduling Synthesis from Synchronous Data-flow Graphs. SAMOS XXI 2021 - 21st International Conference on embedded computer Systems: Architectures, MOdeling and Simulation, Jul 2021, Virtual, France. pp.1-12. ⟨hal-03488217⟩
Accès au texte intégral et bibtex
https://inria.hal.science/hal-03488217/file/R_34_PDF.pdf BibTex

2020

Conference papers

ref_biblio
Alexandre Honorat, Karol Desnos, Mickaël Dardaillon, Jean-François Nezan. A Fast Heuristic to Pipeline SDF Graphs. Embedded Computer Systems: Architectures, Modeling, and Simulation, Jul 2020, Pythagorion, Samos Island, Greece. pp.139-151, ⟨10.1007/978-3-030-60939-9_10⟩. ⟨hal-02993338⟩
Accès au texte intégral et bibtex
https://hal.science/hal-02993338/file/main.pdf BibTex
ref_biblio
Alexandre Honorat, Karol Desnos, Shuvra S Bhattacharyya, Jean-François Nezan. Scheduling of Synchronous Dataflow Graphs with Partially Periodic Real-Time Constraints. Real-Time Networks and Systems, Jun 2020, Paris, France. ⟨10.1145/3394810.3394820⟩. ⟨hal-02883663⟩
Accès au texte intégral et bibtex
https://hal.science/hal-02883663/file/main.pdf BibTex

Theses

ref_biblio
Alexandre Honorat. Modeling, Scheduling, Pipelining and Configuration of Synchronous Dataflow Graphs with Throughput Constraints. Signal and Image processing. INSA de Rennes, 2020. English. ⟨NNT : 2020ISAR0010⟩. ⟨tel-03337988⟩
Accès au texte intégral et bibtex
https://theses.hal.science/tel-03337988/file/2020ISAR0010_HONORAT_Alexandre_TheseDEF_attestCorrections.pdf BibTex

2019

Journal articles

ref_biblio
Thierry Gautier, Clément Guy, Alexandre Honorat, Paul Le Guernic, Jean-Pierre Talpin, et al.. Polychronous automata and their use for formal validation of AADL models. Frontiers of Computer Science, 2019, 13 (4), pp.677-697. ⟨10.1007/s11704-017-6134-5⟩. ⟨hal-01411257⟩
Accès au texte intégral et bibtex
https://inria.hal.science/hal-01411257/file/extended_tase15.pdf BibTex

Conference papers

ref_biblio
Hai Nam Tran, Alexandre Honorat, Jean-Pierre Talpin, Thierry Gautier, Loïc Besnard. Efficient Contention-Aware Scheduling of SDF Graphs on Shared Multi-bank Memory. ICECCS 2019 - 24th International Conference on Engineering of Complex Computer Systems, Nov 2019, Hong Kong, China. pp.114-123, ⟨10.1109/ICECCS.2019.00020⟩. ⟨hal-02193639v2⟩
Accès au texte intégral et bibtex
https://inria.hal.science/hal-02193639/file/iceccs19.pdf BibTex
ref_biblio
Alexandre Honorat, Karol Desnos, Maxime Pelcat, Jean-François Nezan. Modeling Nested for Loops with Explicit Parallelism in Synchronous DataFlow Graphs. Embedded Computer Systems: Architectures, Modeling, and Simulation, Jul 2019, Pythagorion, Samos Island, Greece. pp.269-280, ⟨10.1007/978-3-030-27562-4_19⟩. ⟨hal-02267487v2⟩
Accès au texte intégral et bibtex
https://hal.science/hal-02267487/file/main.pdf BibTex

2017

Conference papers

ref_biblio
Alexandre Honorat, Hai Nam Tran, Loïc Besnard, Thierry Gautier, Jean-Pierre Talpin, et al.. ADFG: a scheduling synthesis tool for dataflow graphs in real-time systems. International Conference on Real-Time Networks and Systems , Oct 2017, Grenoble, France. pp.1-10, ⟨10.1145/3139258.3139267⟩. ⟨hal-01615142⟩
Accès au texte intégral et bibtex
https://inria.hal.science/hal-01615142/file/rnts17.pdf BibTex

2016

Conference papers

ref_biblio
Olivier Aumage, Denis Barthou, Alexandre Honorat. A Stencil DSEL for Single Code Accelerated Computing with SYCL. SYCL 2016 1st SYCL Programming Workshop during the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, Mar 2016, Barcelone, Spain. ⟨hal-01290099⟩
Accès au texte intégral et bibtex
https://hal.science/hal-01290099/file/main.pdf BibTex